Load–store architecture
load 对应的是read data from memory；
store 对应的是write data to memory；
wikipedia Load–store architecture
In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers), and ALU operations (which only occur between registers).[1]:9-12
NOTE: 显然，在 load–store architecture 中，所有的operand必须要先load到ALU中，ALU在执行指令的过程中，是不会access memory的；在ALU运算完成后，就将计算的结果store到memory中；
RISC instruction set architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.[1]:9–12
For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register–memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register.[1]:9–12
The earliest example of a load–store architecture was the CDC 6600.[1]:54–56 Almost all vector processors (including many GPUs[2]) use the load–store approach.[3]
See also
chortle Load and Store
The operands for all arithmetic and logic operations are contained in registers. To operate on data in main memory, the data is first copied into registers. A load operation copies data from main memory into a register. A store operation copies data from a register into main memory .
When a word (4 bytes) is loaded or stored the memory address must be a multiple of four. This is called an alignment restriction. Addresses that are a multiple of four are called word aligned. This restriction makes the hardware simpler and faster.
The lw instruction loads a word into a register from memory. The sw instruction stores a word from a register into memory. Each instruction specifies a register and a memory address (details in a few pages).
reading list
https://azeria-labs.com/memory-instructions-load-and-store-part-4/